Room: 1.162, Bldg: EV, 1515 Ste-Catherine West, Montreal, Quebec, Canada, H3G1M8

Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. Previously reserved for communication over 100’s of kilometres, today optical links are widely viewed as the primary solution for chip-to-chip links above 100 Gbps and up to 1 km. Meanwhile, CMOS technology scaling has led us toward integrated circuit transceivers that are, essentially, complete modems: thin but critical analog front-end circuits and a large custom DSP. This presentation will describe how to co-design of DSP transceivers with a thin but critical analog front-end and the associated optical components to create optical links serving future datacentre communication needs. As an example, a 4-PAM CMOS linear TIA designed in a FinFET technology consuming less than 50 mW and co-packaged alongside photodiodes is presented. The circuits and packaging are co-designed to maximize the passive front-end BW. Experimental results confirm the integrated optical fibre receiver operates up to 160-Gb/s using a single wavelength with a suitable DSP. Speaker(s): Dr. Tony Chan Carusone, Room: 1.162, Bldg: EV, 1515 Ste-Catherine West, Montreal, Quebec, Canada, H3G1M8